The fabrication of various solid state devices requires the use of planar substrates, or semiconductor wafers, on which integrated circuits are fabricated. The final number, or yield, of functional integrated circuits on a wafer at the end of the IC fabrication process is of utmost importance to semiconductor manufacturers, and increasing the yield of circuits on the wafer is the main goal of semiconductor fabrication. After packaging, the circuits on the wafers are tested, wherein non-functional dies are marked using an inking process and the functional dies on the wafer are separated and sold. IC fabricators increase the yield of dies on a wafer by exploiting economies of scale. Over 1000 dies may be formed on a single wafer which measures from six to twelve inches in diameter.
Various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby etching the conducting layer in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
The numerous processing steps outlined above are used to cumulatively apply multiple electrically conductive and insulative layers on the wafer and pattern the layers to form the circuits. The final yield of functional circuits on the wafer depends on proper application of each layer during the process steps. Proper application of those layers depends, in turn, on coating the material in a uniform spread over the surface of the wafer in an economical and efficient manner. The various layers define circuit components or devices such as transistors.
After the individual devices have been fabricated on the substrate, they must be connected together to perform the desired circuit functions. This interconnection process is generally known as “metallization” and is performed using a number of different photolithographic, deposition, and removal techniques. In one interconnection process, called a “dual damascene” technique, two interconnect channels of conductor materials are separated by interlayer dielectric layers in vertically separated planes perpendicular to each other and interconnected by a vertical connection, or “via”, at their closest point.
In the dual damascene process, the vias and the trenches are etched in the same step, and the etch stop layer defines the bottom of the trenches. In other variations, the trench is patterned and etched after the via. In the single damascene process, the vias and trenches are individually, rather than simultaneously, filled with copper inlays.
In the semiconductor industry, aluminum has been frequently used in the past as a metal film for forming lines or wiring, due to the electrical advantages of aluminum including conductivity, ohmic contact property to silicon, wire bonding property, and processibility. Multilevel metal oxide semiconductor (MOS) device technology continues to evolve with the development of faster and more reliable MOS devices. Currently, there is a drive to replace aluminum metallization, tungsten interconnection and titanium and titanium nitride barrier layer fabrication with copper. In multilevel metallization using copper, the crystallographic structure of the metal layers and the nucleation of grain size and structure will have an increasing effect on the quality and yield of device products.
A cross-section of a conventional metallization structure 10 for connecting devices on a semiconductor substrate 12 is shown in FIG. 1. The structure 10 includes a conductive line 18, such as copper, deposited on the substrate 12. A dielectric layer 14 overlies the substrate 12 and the conductive line 18. A via 16, filled with a conductive material 20 such as copper, extends through the dielectric layer 14 and contacts the conductive line 18. A metal line 22 is deposited on the dielectric layer 14 and lies in contact with the conductive material 20. The metal line 22 provides electrical contact between the conductive line 18 and an integrated circuit device (not shown) fabricated on the substrate 12.
During current flow through the conductive line 18, conductive material 20 and metal line 22, electrons flow through these elements in the direction of the predominant current flow. Over time, the flowing electrons cause material transport of the metal in the elements. This electromigration of the metal atoms, in combination with repeated thermal cycles applied to the elements, may eventually cause the metal line 22 to pull away from the conductive material 20, breaking contact between the metal line 22 and the conductive line 18, as shown in FIG. 2.
The medium-time-to-failure (MTF), which is the medium time which elapses between initial onset of current flow and electromigration-induced failure, is believed to be related to the grain size in the metal film; the distribution of grains in the film; the degree to which the metal in the conductive material or metal line approximates the <111> crystal orientation texture; and the method of film deposition and line width. Copper interconnect lines having a relatively high ratio of lower-angle grain boundaries have been shown to have a high MTF. In other words, copper interconnect lines which have a highly-aligned grain or crystal orientation have exhibited a high MTF. The copper <111> crystal orientation texture is characterized by a highly-aligned crystal orientation. Therefore, copper materials having the <111> crystal orientation texture have a relatively high MTF.
In the conventional process for fabricating a conventional metallization structure 10 on a substrate 12, the conductive material 20 is deposited in the via 16 and the metal line 22 is deposited on the dielectric layer 14, typically using electroplating techniques. The conductive material 20 and metal line 22 are then subjected to CMP and annealed typically using heated nitrogen gas in a thermal processing furnace. However, during the annealing process, the copper crystal orientation texture is altered from the highly-aligned and packed <111> crystal orientation texture to a more randomly-oriented orientation texture. This substantially decreases the MTF of the metal line 22. Accordingly, a novel treatment method is needed for re-orienting the crystal orientation texture of a conductive metal to a <111> orientation texture in order to increase the MTF of the metal.
An object of the present invention is to provide a novel plasma treatment method for the reduction of electromigration in a metal.
Another object of the present invention is to provide a novel plasma treatment method which is capable of prolonging the lifetime of metal interconnects fabricated on a semiconductor substrate.
Still another object of the present invention is to provide a novel plasma treatment method which is capable of increasing the MTF (mean-time-to-failure) of metal interconnect layers in a semiconductor device.
Yet another object of the present invention is to provide a novel plasma treatment method which includes the plasma treatment of a metal electroplated into a trench opening in order to provide a crystal orientation texture which at least approximates the <111> crystal orientation texture of the metal.